1. Technical Field
The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device formed by directly connecting a solder ball of an upper package to a pad of a lower package and a manufacturing method thereof.
2. Background Art
There is a Package on Package (PoP) technique as one of the important element techniques for downsizing, thinning, etc. in electronic equipment. As a typical example of the PoP technique, a configuration of directly connecting a solder ball of an upper package to a pad of a lower package is given, and a semiconductor device with high density and high performance can be achieved.
In the PoP technique, accuracy of recognition of a package position in the case of mutually bonding packages has an influence on quality of a semiconductor device, so that the accuracy becomes very important. Here, JP-A-9-321086 discloses an example of a manufacturing method of a conventional semiconductor device (see FIG. 6). According to the method, metal wirings 121, 122, . . . are formed on a mounting substrate 111, and an insulating layer 113 where an opening 114 intersecting with each of the metal wirings 121, 122, . . . is formed is formed. Together with the metal wirings 121, 122, . . . , a first square alignment mark 116 is formed and also an opening for partially overlapping with this alignment mark 116 is formed in the insulating layer 113 to form a second alignment mark 117. Pads 151, 152, . . . are formed at intersections of the opening 114 with each of the metal wirings 121, 122, . . . to form a bump electrode, and a displacement of the pads 151, 152, . . . can be recognized by recognition of a displacement of the identified corners (corner A, corner B) of the alignment marks 116 and 117.
Further, JP-A-2005-93839 discloses as another example of a manufacturing method of the conventional semiconductor device (see FIG. 7). According to the method, a circuit element having an electrode on one principal surface and a substrate 201 having an electrode 203 for a recognition bump 213 and an electrode 202 for a connection bump 212 disposed on one principal surface are prepared, and the connection bump 212 and the recognition bump 213 are respectively formed in the electrode 202 and the electrode 203 using a wire bonding method. Based on an image of the recognition bump 213 photographed using optical means, a position of the recognition bump 213 is detected and, based on the position, the circuit element is bonded on the substrate 201 through the connection bump 212. Since the top of the recognition bump 213 has a protrusion shape, it is easy to obtain contrast to the electrode 203 and thus a position of the recognition bump 213 can be detected accurately. (See e.g., JP-A-9-321086 and JP-A-2005-93839)
Nowadays, downsizing and thinning in electronic equipment are more advancing and a demand for downsizing and density growth in a semiconductor device is more increasing. However, in the PoP technique for downsizing the semiconductor device, for example, like the conventional semiconductor device shown in FIG. 7, the configuration where the recognition bump etc. for recognizing a package position in a manufacturing process hinders downsizing of the semiconductor device.